NRF24L01 SPI Register Mask Definitions

More...

Macros
#define	NRF24L01_RX_PW_P0_MASK_REG   (uint8_t) NRF24L01_RX_PW_P0_REG_BITS_RX_PW_P0
#define	NRF24L01_RX_PW_P1_MASK_REG   (uint8_t) NRF24L01_RX_PW_P1_REG_BITS_RX_PW_P1
#define	NRF24L01_RX_PW_P2_MASK_REG   (uint8_t) NRF24L01_RX_PW_P2_REG_BITS_RX_PW_P2
#define	NRF24L01_RX_PW_P3_MASK_REG   (uint8_t) NRF24L01_RX_PW_P3_REG_BITS_RX_PW_P3
#define	NRF24L01_RX_PW_P4_MASK_REG   (uint8_t) NRF24L01_RX_PW_P4_REG_BITS_RX_PW_P4
#define	NRF24L01_RX_PW_P5_MASK_REG   (uint8_t) NRF24L01_RX_PW_P5_REG_BITS_RX_PW_P5
#define	NRF24L01_FIFO_STATUS_MASK_REG
	Mask for all defined bits in FIFO_STATUS register. More...
#define	NRF24L01_FIFO_STATUS_MASK_RX_FLAGS
	Mask for RX_FIFO[1:0] status bits in FIFO_STATUS register. More...
#define	NRF24L01_FIFO_STATUS_MASK_TX_FLAGS
	Mask for TX_FIFO[6:4] status bits in FIFO_STATUS register. More...
#define	NRF24L01_DYNPD_MASK_REG
	Mask for DPL_Px[5:0] bits in DYNPD feature register. More...
#define	NRF24L01_FEATURE_MASK_REG

Configuration Register (CONFIG)
Provides a register mask, an interrupt mask and a CRC mask View details in datasheet for more information
#define	NRF24L01_CONFIG_MASK_REG
	< Mask for all defined bits[6:0] in CONFIG register More...
#define	NRF24L01_CONFIG_MASK_INTERRUPT_MASKS
	Mask for CRC[3:2] bits in CONFIG register. More...
#define	NRF24L01_CONFIG_MASK_CRC
	RX_DR[6] bit in CONFIG register. More...

Enhanced ShockBurst™ Enable Register (EN_AA)
Provides a register mask View details in datasheet for more information
#define	NRF24L01_EN_AA_MASK_REG
	Mask for all defined bits[5:0] in EN_AA register. More...

RX Pipe Enable Register (EN_RXADDR)
Provides a register mask View details in datasheet for more information
#define	NRF24L01_EN_RXADDR_MASK_REG
	Mask for all defined bits[5:0] in EN_RXADDR register. More...

Pipe Address Width Common Configuration Register (SETUP_AW)
Provides a register mask View details in datasheet for more information
#define	NRF24L01_SETUP_AW_MASK_REG   (uint8_t) NRF24L01_SETUP_AW_REG_BITS_AW
	Mask for all defined bits[1:0] in AW register. More...

Automatic Retransmission Configuration Register (SETUP_RETR)
Provides a register mask View details in datasheet for more information
#define	NRF24L01_SETUP_RETR_MASK_REG
	Mask for all defined bits[7:0] in SETUP_RETR register. More...

RF Channel Configuration Register (RF_CH)
Provides a register mask View details in datasheet for more information
#define	NRF24L01_RF_CH_MASK_REG   (uint8_t) NRF24L01_RF_CH_REG_BITS_RF_CH
	Mask for all defined bits[6:0] in RF_CH register. More...

RF Configuration Register (RF_SETUP)
Provides a register mask View details in datasheet for more information
#define	NRF24L01_RF_SETUP_MASK_REG
	Mask for all defined bits[4:0] in RF_SETUP register. More...

Device Status Register (STATUS)
Provides a register mask and an IRQ flags mask View details in datasheet for more information
#define	NRF24L01_STATUS_MASK_REG
	Mask for all defined bits[6:0] in STATUS register. More...
#define	NRF24L01_STATUS_MASK_IRQ_FLAGS
	Mask for IRQ[6:4] interrupt flag bits in STATUS register. More...

Transmission Observation Register (OBSERVE_TX)
Provides a register mask View details in datasheet for more information
#define	NRF24L01_OBSERVE_TX_MASK_REG
	Mask for all defined bits[7:0] in OBSERVE_TX register. More...

Carrier Detect Register (CD)
Provides a register mask View details in datasheet for more information
#define	NRF24L01_CD_MASK_REG   (uint8_t) NRF24L01_CD_REG_BIT_CD
	Mask for all defined bits[0:0] in CD register. More...

Detailed Description

These definitions should be used when trying to mask out on or more properties of the NRF24L01. For individual bit definitions see NRF24L01 SPI Register Bit Definitions

The naming convention for all definitions is NRF24L01_r_MASK_x where r is the register name where the bit is found and x an arbitrary assigned name Each register also has a full mask defined for it under the name NRF24L01_r_MASK_REG

Macro Definition Documentation

NRF24L01_CD_MASK_REG

#define NRF24L01_CD_MASK_REG   (uint8_t) NRF24L01_CD_REG_BIT_CD

Mask for all defined bits[0:0] in CD register.

NRF24L01_CONFIG_MASK_CRC

#define NRF24L01_CONFIG_MASK_CRC

Value:

    (uint8_t)( \
    NRF24L01_CONFIG_REG_BIT_EN_CRC |        \
    NRF24L01_CONFIG_REG_BIT_CRCO)

RX_DR[6] bit in CONFIG register.

NRF24L01_CONFIG_MASK_INTERRUPT_MASKS

#define NRF24L01_CONFIG_MASK_INTERRUPT_MASKS

Value:

    (uint8_t)( \
    NRF24L01_CONFIG_REG_BIT_MASK_RX_DR |                \
    NRF24L01_CONFIG_REG_BIT_MASK_TX_DS |                \
    NRF24L01_CONFIG_REG_BIT_MASK_MAX_RT)

Mask for CRC[3:2] bits in CONFIG register.

NRF24L01_CONFIG_MASK_REG

#define NRF24L01_CONFIG_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_CONFIG_REG_BIT_MASK_RX_DR |                   \
    NRF24L01_CONFIG_REG_BIT_MASK_TX_DS |                   \
    NRF24L01_CONFIG_REG_BIT_MASK_MAX_RT |                  \
    NRF24L01_CONFIG_REG_BIT_EN_CRC |                       \
    NRF24L01_CONFIG_REG_BIT_CRCO |                         \
    NRF24L01_CONFIG_REG_BIT_PWR_UP |                       \
    NRF24L01_CONFIG_REG_BIT_PRIM_RX)

< Mask for all defined bits[6:0] in CONFIG register

Mask for INTERRUPT[6:4] bits in CONFIG register

NRF24L01_DYNPD_MASK_REG

#define NRF24L01_DYNPD_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_DYNPD_REG_BIT_DPL_P5 |        \
    NRF24L01_DYNPD_REG_BIT_DPL_P4 |        \
    NRF24L01_DYNPD_REG_BIT_DPL_P3 |        \
    NRF24L01_DYNPD_REG_BIT_DPL_P2 |        \
    NRF24L01_DYNPD_REG_BIT_DPL_P1 |        \
    NRF24L01_DYNPD_REG_BIT_DPL_P0)

Mask for DPL_Px[5:0] bits in DYNPD feature register.

NRF24L01_EN_AA_MASK_REG

#define NRF24L01_EN_AA_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_EN_AA_REG_BIT_ENAA_P5 |       \
    NRF24L01_EN_AA_REG_BIT_ENAA_P4 |       \
    NRF24L01_EN_AA_REG_BIT_ENAA_P3 |       \
    NRF24L01_EN_AA_REG_BIT_ENAA_P2 |       \
    NRF24L01_EN_AA_REG_BIT_ENAA_P1 |       \
    NRF24L01_EN_AA_REG_BIT_ENAA_P0)

Mask for all defined bits[5:0] in EN_AA register.

NRF24L01_EN_RXADDR_MASK_REG

#define NRF24L01_EN_RXADDR_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_EN_RXADDR_REG_BIT_ERX_P5 |        \
    NRF24L01_EN_RXADDR_REG_BIT_ERX_P4 |        \
    NRF24L01_EN_RXADDR_REG_BIT_ERX_P3 |        \
    NRF24L01_EN_RXADDR_REG_BIT_ERX_P2 |        \
    NRF24L01_EN_RXADDR_REG_BIT_ERX_P1 |        \
    NRF24L01_EN_RXADDR_REG_BIT_ERX_P0)

Mask for all defined bits[5:0] in EN_RXADDR register.

NRF24L01_FEATURE_MASK_REG

#define NRF24L01_FEATURE_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_FEATURE_REG_BIT_EN_DPL |        \
    NRF24L01_FEATURE_REG_BIT_EN_ACK_PAY |    \
    NRF24L01_FEATURE_REG_BIT_EN_DYN_ACK)

NRF24L01_FIFO_STATUS_MASK_REG

#define NRF24L01_FIFO_STATUS_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_FIFO_STATUS_REG_BIT_TX_REUSE |      \
    NRF24L01_FIFO_STATUS_REG_BIT_TX_FULL |       \
    NRF24L01_FIFO_STATUS_REG_BIT_TX_EMPTY |      \
    NRF24L01_FIFO_STATUS_REG_BIT_RX_FULL |       \
    NRF24L01_FIFO_STATUS_REG_BIT_RX_EMPTY)

Mask for all defined bits in FIFO_STATUS register.

NRF24L01_FIFO_STATUS_MASK_RX_FLAGS

#define NRF24L01_FIFO_STATUS_MASK_RX_FLAGS

Value:

    (uint8_t)( \
    NRF24L01_FIFO_STATUS_REG_BIT_RX_FULL |            \
    NRF24L01_FIFO_STATUS_REG_BIT_RX_EMPTY)

Mask for RX_FIFO[1:0] status bits in FIFO_STATUS register.

NRF24L01_FIFO_STATUS_MASK_TX_FLAGS

#define NRF24L01_FIFO_STATUS_MASK_TX_FLAGS

Value:

    (uint8_t)( \
    NRF24L01_FIFO_STATUS_REG_BIT_TX_REUSE |           \
    NRF24L01_FIFO_STATUS_REG_BIT_TX_FULL |            \
    NRF24L01_FIFO_STATUS_REG_BIT_TX_EMPTY)

Mask for TX_FIFO[6:4] status bits in FIFO_STATUS register.

NRF24L01_OBSERVE_TX_MASK_REG

#define NRF24L01_OBSERVE_TX_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_OBSERVE_TX_REG_BITS_PLOS_CNT |     \
    NRF24L01_OBSERVE_TX_REG_BITS_ARC_CNT)

Mask for all defined bits[7:0] in OBSERVE_TX register.

NRF24L01_RF_CH_MASK_REG

#define NRF24L01_RF_CH_MASK_REG   (uint8_t) NRF24L01_RF_CH_REG_BITS_RF_CH

Mask for all defined bits[6:0] in RF_CH register.

NRF24L01_RF_SETUP_MASK_REG

#define NRF24L01_RF_SETUP_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_RF_SETUP_REG_BIT_PLL_LOCK |      \
    NRF24L01_RF_SETUP_REG_BIT_RF_DR |         \
    NRF24L01_RF_SETUP_REG_BITS_RF_PWR |       \
    NRF24L01_RF_SETUP_REG_BIT_LNA_HCURR)

Mask for all defined bits[4:0] in RF_SETUP register.

NRF24L01_RX_PW_P0_MASK_REG

#define NRF24L01_RX_PW_P0_MASK_REG   (uint8_t) NRF24L01_RX_PW_P0_REG_BITS_RX_PW_P0

NRF24L01_RX_PW_P1_MASK_REG

#define NRF24L01_RX_PW_P1_MASK_REG   (uint8_t) NRF24L01_RX_PW_P1_REG_BITS_RX_PW_P1

NRF24L01_RX_PW_P2_MASK_REG

#define NRF24L01_RX_PW_P2_MASK_REG   (uint8_t) NRF24L01_RX_PW_P2_REG_BITS_RX_PW_P2

NRF24L01_RX_PW_P3_MASK_REG

#define NRF24L01_RX_PW_P3_MASK_REG   (uint8_t) NRF24L01_RX_PW_P3_REG_BITS_RX_PW_P3

NRF24L01_RX_PW_P4_MASK_REG

#define NRF24L01_RX_PW_P4_MASK_REG   (uint8_t) NRF24L01_RX_PW_P4_REG_BITS_RX_PW_P4

NRF24L01_RX_PW_P5_MASK_REG

#define NRF24L01_RX_PW_P5_MASK_REG   (uint8_t) NRF24L01_RX_PW_P5_REG_BITS_RX_PW_P5

NRF24L01_SETUP_AW_MASK_REG

#define NRF24L01_SETUP_AW_MASK_REG   (uint8_t) NRF24L01_SETUP_AW_REG_BITS_AW

Mask for all defined bits[1:0] in AW register.

NRF24L01_SETUP_RETR_MASK_REG

#define NRF24L01_SETUP_RETR_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_SETUP_RETR_REG_BITS_ARD |          \
    NRF24L01_SETUP_RETR_REG_BITS_ARC)

Mask for all defined bits[7:0] in SETUP_RETR register.

NRF24L01_STATUS_MASK_IRQ_FLAGS

#define NRF24L01_STATUS_MASK_IRQ_FLAGS

Value:

    (uint8_t)( \
    NRF24L01_STATUS_REG_BIT_RX_DR |               \
    NRF24L01_STATUS_REG_BIT_TX_DS |               \
    NRF24L01_STATUS_REG_BIT_MAX_RT)

Mask for IRQ[6:4] interrupt flag bits in STATUS register.

NRF24L01_STATUS_MASK_REG

#define NRF24L01_STATUS_MASK_REG

Value:

    (uint8_t)( \
    NRF24L01_STATUS_REG_BIT_RX_DR |         \
    NRF24L01_STATUS_REG_BIT_TX_DS |         \
    NRF24L01_STATUS_REG_BIT_MAX_RT |        \
    NRF24L01_STATUS_REG_BITS_RX_P_NO |      \
    NRF24L01_STATUS_REG_BIT_TX_FULL)

Mask for all defined bits[6:0] in STATUS register.