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nrf24l01
Driver for the nRF24L01(+) transceiver
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Configuration Register (CONFIG) | |
Provides a register mask, an interrupt mask and a CRC mask View details in datasheet for more information | |
| #define | NRF24L01_CONFIG_REG_BIT_MASK_RX_DR (uint8_t)0x40 |
| RX_DR[6] bit in CONFIG register. More... | |
| #define | NRF24L01_CONFIG_REG_BIT_MASK_TX_DS (uint8_t)0x20 |
| TX_DS[5] bit in CONFIG register. More... | |
| #define | NRF24L01_CONFIG_REG_BIT_MASK_MAX_RT (uint8_t)0x10 |
| MAX_RT[4] bit in CONFIG register. More... | |
| #define | NRF24L01_CONFIG_REG_BIT_EN_CRC (uint8_t)0x08 |
| EN_CRC[3] bit in CONFIG register. More... | |
| #define | NRF24L01_CONFIG_REG_BIT_CRCO (uint8_t)0x04 |
| CRCO[2] bit in CONFIG register. More... | |
| #define | NRF24L01_CONFIG_REG_BIT_PWR_UP (uint8_t)0x02 |
| PWR_UP[1] bit in CONFIG register. More... | |
| #define | NRF24L01_CONFIG_REG_BIT_PRIM_RX (uint8_t)0x01 |
| PRIM_RX[0] bit in CONFIG register. More... | |
| #define | NRF24L01_CONFIG_MASK_REG |
| < Mask for all defined bits[6:0] in CONFIG register More... | |
| #define | NRF24L01_CONFIG_MASK_INTERRUPT_MASKS |
| Mask for CRC[3:2] bits in CONFIG register. More... | |
| #define | NRF24L01_CONFIG_MASK_CRC |
| RX_DR[6] bit in CONFIG register. More... | |
Enhanced ShockBurst™ Enable Register (EN_AA) | |
|
View details in datasheet for more information | |
| #define | NRF24L01_EN_AA_REG_BIT_ENAA_P5 (uint8_t)0x20 |
| ENAA_P5[5] bit in EN_AA register. More... | |
| #define | NRF24L01_EN_AA_REG_BIT_ENAA_P4 (uint8_t)0x10 |
| ENAA_P4[4] bit in EN_AA register. More... | |
| #define | NRF24L01_EN_AA_REG_BIT_ENAA_P3 (uint8_t)0x08 |
| ENAA_P3[3] bit in EN_AA register. More... | |
| #define | NRF24L01_EN_AA_REG_BIT_ENAA_P2 (uint8_t)0x04 |
| ENAA_P2[2] bit in EN_AA register. More... | |
| #define | NRF24L01_EN_AA_REG_BIT_ENAA_P1 (uint8_t)0x02 |
| ENAA_P1[1] bit in EN_AA register. More... | |
| #define | NRF24L01_EN_AA_REG_BIT_ENAA_P0 (uint8_t)0x01 |
| ENAA_P0[0] bit in EN_AA register. More... | |
| #define | NRF24L01_EN_AA_MASK_REG |
| Mask for all defined bits[5:0] in EN_AA register. More... | |
RX Pipe Enable Register (EN_RXADDR) | |
|
View details in datasheet for more information | |
| #define | NRF24L01_EN_RXADDR_REG_BIT_ERX_P5 (uint8_t)0x20 |
| Mask for all defined bits[5:0] in EN_RXADDR register. More... | |
| #define | NRF24L01_EN_RXADDR_REG_BIT_ERX_P4 (uint8_t)0x10 |
| Mask for all defined bits[5:0] in EN_RXADDR register. More... | |
| #define | NRF24L01_EN_RXADDR_REG_BIT_ERX_P3 (uint8_t)0x08 |
| Mask for all defined bits[5:0] in EN_RXADDR register. More... | |
| #define | NRF24L01_EN_RXADDR_REG_BIT_ERX_P2 (uint8_t)0x04 |
| Mask for all defined bits[5:0] in EN_RXADDR register. More... | |
| #define | NRF24L01_EN_RXADDR_REG_BIT_ERX_P1 (uint8_t)0x02 |
| Mask for all defined bits[5:0] in EN_RXADDR register. More... | |
| #define | NRF24L01_EN_RXADDR_REG_BIT_ERX_P0 (uint8_t)0x01 |
| Mask for all defined bits[5:0] in EN_RXADDR register. More... | |
| #define | NRF24L01_EN_RXADDR_MASK_REG |
| Mask for all defined bits[5:0] in EN_RXADDR register. More... | |
Pipe Address Width Common Configuration Register (SETUP_AW) | |
|
View details in datasheet for more information | |
| #define | NRF24L01_SETUP_AW_REG_BITS_AW (uint8_t)0x03 |
| AW[1:0] bits in SETUP_AW register. More... | |
| #define | NRF24L01_SETUP_AW_MASK_REG (uint8_t) NRF24L01_SETUP_AW_REG_BITS_AW |
| Mask for all defined bits[1:0] in AW register. More... | |
Automatic Retransmission Configuration Register (SETUP_RETR) | |
|
View details in datasheet for more information | |
| #define | NRF24L01_SETUP_RETR_REG_BITS_ARD (uint8_t)0xF0 |
| ARD[7:4] bits in SETUP_RETR register. More... | |
| #define | NRF24L01_SETUP_RETR_REG_BITS_ARC (uint8_t)0x0F |
| ARC[3:0] bits in SETUP_RETR register. More... | |
| #define | NRF24L01_SETUP_RETR_MASK_REG |
| Mask for all defined bits[7:0] in SETUP_RETR register. More... | |
RF Channel Configuration Register (RF_CH) | |
|
View details in datasheet for more information | |
| #define | NRF24L01_RF_CH_REG_BITS_RF_CH (uint8_t)0x7F |
| RF_CH[6:0] bits in RF_CH register. More... | |
| #define | NRF24L01_RF_CH_MASK_REG (uint8_t) NRF24L01_RF_CH_REG_BITS_RF_CH |
| Mask for all defined bits[6:0] in RF_CH register. More... | |
RF Configuration Register (RF_SETUP) | |
|
View details in datasheet for more information | |
| #define | NRF24L01_RF_SETUP_REG_BIT_PLL_LOCK (uint8_t)0x10 |
| PLL_LOCK[5] bit in RF_SETUP register. More... | |
| #define | NRF24L01_RF_SETUP_REG_BIT_RF_DR (uint8_t)0x08 |
| RF_DR[4] bit in RF_SETUP register. More... | |
| #define | NRF24L01_RF_SETUP_REG_BITS_RF_PWR (uint8_t)0x06 |
| RF_PWR[2:1] bits in RF_SETUP register. More... | |
| #define | NRF24L01_RF_SETUP_REG_BIT_LNA_HCURR (uint8_t)0x01 |
| LNA_HCURR[0] bit in RF_SETUP register. More... | |
| #define | NRF24L01_RF_SETUP_MASK_REG |
| Mask for all defined bits[4:0] in RF_SETUP register. More... | |
Device Status Register (STATUS) | |
Provides a register mask and an IRQ flags mask View details in datasheet for more information | |
| #define | NRF24L01_STATUS_REG_BIT_RX_DR (uint8_t)0x40 |
| RX_DR[6] interrupt flag bit in STATUS register. More... | |
| #define | NRF24L01_STATUS_REG_BIT_TX_DS (uint8_t)0x20 |
| TX_DS[5] interrupt flag bit in STATUS register. More... | |
| #define | NRF24L01_STATUS_REG_BIT_MAX_RT (uint8_t)0x10 |
| MAX_RT[4] interrupt flag bit in STATUS register. More... | |
| #define | NRF24L01_STATUS_REG_BITS_RX_P_NO (uint8_t)0x0E |
| RX_P_NO[3:1] pipe number bits in STATUS register. More... | |
| #define | NRF24L01_STATUS_REG_BIT_TX_FULL (uint8_t)0x01 |
| TX_FULL[0] flag bit in STATUS register. More... | |
| #define | NRF24L01_STATUS_MASK_REG |
| Mask for all defined bits[6:0] in STATUS register. More... | |
| #define | NRF24L01_STATUS_MASK_IRQ_FLAGS |
| Mask for IRQ[6:4] interrupt flag bits in STATUS register. More... | |
Transmission Observation Register (OBSERVE_TX) | |
|
View details in datasheet for more information | |
| #define | NRF24L01_OBSERVE_TX_REG_BITS_PLOS_CNT (uint8_t)0xF0 |
| PLOS_CNT[7:4] lost packet count bits in OBSERVE_TX register. More... | |
| #define | NRF24L01_OBSERVE_TX_REG_BITS_ARC_CNT (uint8_t)0x0F |
| ARC_CNT[3:0] resent packet count bits in OBSERVE_TX register. More... | |
| #define | NRF24L01_OBSERVE_TX_MASK_REG |
| Mask for all defined bits[7:0] in OBSERVE_TX register. More... | |
Carrier Detect Register (CD) | |
|
View details in datasheet for more information | |
| #define | NRF24L01_CD_REG_BIT_CD (uint8_t)0x01 |
| CD[0] bit in CD register. More... | |
| #define | NRF24L01_CD_MASK_REG (uint8_t) NRF24L01_CD_REG_BIT_CD |
| Mask for all defined bits[0:0] in CD register. More... | |
RX Pipe 0 Payload Width Register (RX_PW_P0) | |
Contains the number of bytes in RX payload in data pipe 0 (1 to 32 bytes) View details in datasheet for more information | |
| #define | NRF24L01_RX_PW_P0_REG_BITS_RX_PW_P0 (uint8_t)0x3F |
| RX_PW_P0[5:0] bits in RX_PW_P0 register. More... | |
RX Pipe 1 Payload Width Register (RX_PW_P1) | |
Contains the number of bytes in RX payload in data pipe 1 (1 to 32 bytes) View details in datasheet for more information | |
| #define | NRF24L01_RX_PW_P1_REG_BITS_RX_PW_P1 (uint8_t)0x3F |
| RX_PW_P1[5:0] bits in RX_PW_P1 register. More... | |
RX Pipe 2 Payload Width Register (RX_PW_P2) | |
Contains the number of bytes in RX payload in data pipe 2 (1 to 32 bytes) View details in datasheet for more information | |
| #define | NRF24L01_RX_PW_P2_REG_BITS_RX_PW_P2 (uint8_t)0x3F |
| RX_PW_P2[5:0] bits in RX_PW_P2 register. More... | |
RX Pipe 3 Payload Width Register (RX_PW_P3) | |
Contains the number of bytes in RX payload in data pipe 3 (1 to 32 bytes) View details in datasheet for more information | |
| #define | NRF24L01_RX_PW_P3_REG_BITS_RX_PW_P3 (uint8_t)0x3F |
| RX_PW_P3[5:0] bits in RX_PW_P3 register. More... | |
RX Pipe 4 Payload Width Register (RX_PW_P4) | |
Contains the number of bytes in RX payload in data pipe 4 (1 to 32 bytes) View details in datasheet for more information | |
| #define | NRF24L01_RX_PW_P4_REG_BITS_RX_PW_P4 (uint8_t)0x3F |
| RX_PW_P4[5:0] bits in RX_PW_P4 register. More... | |
RX Pipe 5 Payload Width Register (RX_PW_P5) | |
Contains the number of bytes in RX payload in data pipe 5 (1 to 32 bytes) View details in datasheet for more information | |
| #define | NRF24L01_RX_PW_P5_REG_BITS_RX_PW_P5 (uint8_t)0x3F |
| RX_PW_P5[5:0] bits in RX_PW_P5 register. More... | |
FIFO Status Register (FIFO_STATUS) | |
Contains the TX packet in reuse flag bit, the TX FIFO full flag bit, the TX FIFO empty flag bit, the RX FIFO full flag bit, and the RX FIFO empty flag bit View details in datasheet for more information | |
| #define | NRF24L01_FIFO_STATUS_REG_BIT_TX_REUSE (uint8_t)0x40 |
| TX_REUSE[5] status bit in FIFO_STATUS register. More... | |
| #define | NRF24L01_FIFO_STATUS_REG_BIT_TX_FULL (uint8_t)0x20 |
| TX_FULL[6] status bit in FIFO_STATUS register. More... | |
| #define | NRF24L01_FIFO_STATUS_REG_BIT_TX_EMPTY (uint8_t)0x10 |
| TX_EMPTY[4] status bits [5:4] in FIFO_STATUS register. More... | |
| #define | NRF24L01_FIFO_STATUS_REG_BIT_RX_FULL (uint8_t)0x02 |
| RX_FULL[1] status bit in FIFO_STATUS register. More... | |
| #define | NRF24L01_FIFO_STATUS_REG_BIT_RX_EMPTY (uint8_t)0x01 |
| RX_EMPTY[0] status bit in FIFO_STATUS register. More... | |
Dynamic Payload Length Enable Configuration Register (DYNPD) | |
Contains the dynamic payload length enable bits for each pipe View details in datasheet for more information | |
| #define | NRF24L01_DYNPD_REG_BIT_DPL_P5 (uint8_t)0x20 |
| #define | NRF24L01_DYNPD_REG_BIT_DPL_P4 (uint8_t)0x10 |
| #define | NRF24L01_DYNPD_REG_BIT_DPL_P3 (uint8_t)0x08 |
| #define | NRF24L01_DYNPD_REG_BIT_DPL_P2 (uint8_t)0x04 |
| #define | NRF24L01_DYNPD_REG_BIT_DPL_P1 (uint8_t)0x02 |
| #define | NRF24L01_DYNPD_REG_BIT_DPL_P0 (uint8_t)0x01 |
Special Feature Register (FEATURE) | |
Contains the enable bits for the NRF24L01 special features View details in datasheet for more information | |
| #define | NRF24L01_FEATURE_REG_BIT_EN_DPL (uint8_t)0x04 |
| EN_DPL[2] bit in FEATURE register. More... | |
| #define | NRF24L01_FEATURE_REG_BIT_EN_ACK_PAY (uint8_t)0x02 |
| EN_ACK_PAY[1] bit in FEATURE register. More... | |
| #define | NRF24L01_FEATURE_REG_BIT_EN_DYN_ACK (uint8_t)0x01 |
| EN_DYN_ACK[0] bit in FEATURE register. More... | |
These definitions should be used when trying to control a specific property of the NRF24L01 which could be represented by one of more bits. For definitions designed for masking see NRF24L01 SPI Register Mask Definitions
The naming convention for all definitions is NRF24L01_r_REG_BIT_x where r is the register name where the bit is found and x is the name assigned to the register bit by the datasheet If register contains a bit field then REG_BIT is pluralized to REG_BITS
| #define NRF24L01_CD_MASK_REG (uint8_t) NRF24L01_CD_REG_BIT_CD |
Mask for all defined bits[0:0] in CD register.
| #define NRF24L01_CD_REG_BIT_CD (uint8_t)0x01 |
CD[0] bit in CD register.
| #define NRF24L01_CONFIG_MASK_CRC |
RX_DR[6] bit in CONFIG register.
| #define NRF24L01_CONFIG_MASK_INTERRUPT_MASKS |
Mask for CRC[3:2] bits in CONFIG register.
| #define NRF24L01_CONFIG_MASK_REG |
< Mask for all defined bits[6:0] in CONFIG register
Mask for INTERRUPT[6:4] bits in CONFIG register
| #define NRF24L01_CONFIG_REG_BIT_CRCO (uint8_t)0x04 |
CRCO[2] bit in CONFIG register.
| #define NRF24L01_CONFIG_REG_BIT_EN_CRC (uint8_t)0x08 |
EN_CRC[3] bit in CONFIG register.
| #define NRF24L01_CONFIG_REG_BIT_MASK_MAX_RT (uint8_t)0x10 |
MAX_RT[4] bit in CONFIG register.
| #define NRF24L01_CONFIG_REG_BIT_MASK_RX_DR (uint8_t)0x40 |
RX_DR[6] bit in CONFIG register.
| #define NRF24L01_CONFIG_REG_BIT_MASK_TX_DS (uint8_t)0x20 |
TX_DS[5] bit in CONFIG register.
| #define NRF24L01_CONFIG_REG_BIT_PRIM_RX (uint8_t)0x01 |
PRIM_RX[0] bit in CONFIG register.
| #define NRF24L01_CONFIG_REG_BIT_PWR_UP (uint8_t)0x02 |
PWR_UP[1] bit in CONFIG register.
| #define NRF24L01_DYNPD_REG_BIT_DPL_P0 (uint8_t)0x01 |
| #define NRF24L01_DYNPD_REG_BIT_DPL_P1 (uint8_t)0x02 |
| #define NRF24L01_DYNPD_REG_BIT_DPL_P2 (uint8_t)0x04 |
| #define NRF24L01_DYNPD_REG_BIT_DPL_P3 (uint8_t)0x08 |
| #define NRF24L01_DYNPD_REG_BIT_DPL_P4 (uint8_t)0x10 |
| #define NRF24L01_DYNPD_REG_BIT_DPL_P5 (uint8_t)0x20 |
| #define NRF24L01_EN_AA_MASK_REG |
Mask for all defined bits[5:0] in EN_AA register.
| #define NRF24L01_EN_AA_REG_BIT_ENAA_P0 (uint8_t)0x01 |
ENAA_P0[0] bit in EN_AA register.
| #define NRF24L01_EN_AA_REG_BIT_ENAA_P1 (uint8_t)0x02 |
ENAA_P1[1] bit in EN_AA register.
| #define NRF24L01_EN_AA_REG_BIT_ENAA_P2 (uint8_t)0x04 |
ENAA_P2[2] bit in EN_AA register.
| #define NRF24L01_EN_AA_REG_BIT_ENAA_P3 (uint8_t)0x08 |
ENAA_P3[3] bit in EN_AA register.
| #define NRF24L01_EN_AA_REG_BIT_ENAA_P4 (uint8_t)0x10 |
ENAA_P4[4] bit in EN_AA register.
| #define NRF24L01_EN_AA_REG_BIT_ENAA_P5 (uint8_t)0x20 |
ENAA_P5[5] bit in EN_AA register.
| #define NRF24L01_EN_RXADDR_MASK_REG |
Mask for all defined bits[5:0] in EN_RXADDR register.
| #define NRF24L01_EN_RXADDR_REG_BIT_ERX_P0 (uint8_t)0x01 |
Mask for all defined bits[5:0] in EN_RXADDR register.
| #define NRF24L01_EN_RXADDR_REG_BIT_ERX_P1 (uint8_t)0x02 |
Mask for all defined bits[5:0] in EN_RXADDR register.
| #define NRF24L01_EN_RXADDR_REG_BIT_ERX_P2 (uint8_t)0x04 |
Mask for all defined bits[5:0] in EN_RXADDR register.
| #define NRF24L01_EN_RXADDR_REG_BIT_ERX_P3 (uint8_t)0x08 |
Mask for all defined bits[5:0] in EN_RXADDR register.
| #define NRF24L01_EN_RXADDR_REG_BIT_ERX_P4 (uint8_t)0x10 |
Mask for all defined bits[5:0] in EN_RXADDR register.
| #define NRF24L01_EN_RXADDR_REG_BIT_ERX_P5 (uint8_t)0x20 |
Mask for all defined bits[5:0] in EN_RXADDR register.
| #define NRF24L01_FEATURE_REG_BIT_EN_ACK_PAY (uint8_t)0x02 |
EN_ACK_PAY[1] bit in FEATURE register.
| #define NRF24L01_FEATURE_REG_BIT_EN_DPL (uint8_t)0x04 |
EN_DPL[2] bit in FEATURE register.
| #define NRF24L01_FEATURE_REG_BIT_EN_DYN_ACK (uint8_t)0x01 |
EN_DYN_ACK[0] bit in FEATURE register.
| #define NRF24L01_FIFO_STATUS_REG_BIT_RX_EMPTY (uint8_t)0x01 |
RX_EMPTY[0] status bit in FIFO_STATUS register.
| #define NRF24L01_FIFO_STATUS_REG_BIT_RX_FULL (uint8_t)0x02 |
RX_FULL[1] status bit in FIFO_STATUS register.
| #define NRF24L01_FIFO_STATUS_REG_BIT_TX_EMPTY (uint8_t)0x10 |
TX_EMPTY[4] status bits [5:4] in FIFO_STATUS register.
| #define NRF24L01_FIFO_STATUS_REG_BIT_TX_FULL (uint8_t)0x20 |
TX_FULL[6] status bit in FIFO_STATUS register.
| #define NRF24L01_FIFO_STATUS_REG_BIT_TX_REUSE (uint8_t)0x40 |
TX_REUSE[5] status bit in FIFO_STATUS register.
| #define NRF24L01_OBSERVE_TX_MASK_REG |
Mask for all defined bits[7:0] in OBSERVE_TX register.
| #define NRF24L01_OBSERVE_TX_REG_BITS_ARC_CNT (uint8_t)0x0F |
ARC_CNT[3:0] resent packet count bits in OBSERVE_TX register.
| #define NRF24L01_OBSERVE_TX_REG_BITS_PLOS_CNT (uint8_t)0xF0 |
PLOS_CNT[7:4] lost packet count bits in OBSERVE_TX register.
| #define NRF24L01_RF_CH_MASK_REG (uint8_t) NRF24L01_RF_CH_REG_BITS_RF_CH |
Mask for all defined bits[6:0] in RF_CH register.
| #define NRF24L01_RF_CH_REG_BITS_RF_CH (uint8_t)0x7F |
RF_CH[6:0] bits in RF_CH register.
| #define NRF24L01_RF_SETUP_MASK_REG |
Mask for all defined bits[4:0] in RF_SETUP register.
| #define NRF24L01_RF_SETUP_REG_BIT_LNA_HCURR (uint8_t)0x01 |
LNA_HCURR[0] bit in RF_SETUP register.
| #define NRF24L01_RF_SETUP_REG_BIT_PLL_LOCK (uint8_t)0x10 |
PLL_LOCK[5] bit in RF_SETUP register.
| #define NRF24L01_RF_SETUP_REG_BIT_RF_DR (uint8_t)0x08 |
RF_DR[4] bit in RF_SETUP register.
| #define NRF24L01_RF_SETUP_REG_BITS_RF_PWR (uint8_t)0x06 |
RF_PWR[2:1] bits in RF_SETUP register.
| #define NRF24L01_RX_PW_P0_REG_BITS_RX_PW_P0 (uint8_t)0x3F |
RX_PW_P0[5:0] bits in RX_PW_P0 register.
| #define NRF24L01_RX_PW_P1_REG_BITS_RX_PW_P1 (uint8_t)0x3F |
RX_PW_P1[5:0] bits in RX_PW_P1 register.
| #define NRF24L01_RX_PW_P2_REG_BITS_RX_PW_P2 (uint8_t)0x3F |
RX_PW_P2[5:0] bits in RX_PW_P2 register.
| #define NRF24L01_RX_PW_P3_REG_BITS_RX_PW_P3 (uint8_t)0x3F |
RX_PW_P3[5:0] bits in RX_PW_P3 register.
| #define NRF24L01_RX_PW_P4_REG_BITS_RX_PW_P4 (uint8_t)0x3F |
RX_PW_P4[5:0] bits in RX_PW_P4 register.
| #define NRF24L01_RX_PW_P5_REG_BITS_RX_PW_P5 (uint8_t)0x3F |
RX_PW_P5[5:0] bits in RX_PW_P5 register.
| #define NRF24L01_SETUP_AW_MASK_REG (uint8_t) NRF24L01_SETUP_AW_REG_BITS_AW |
Mask for all defined bits[1:0] in AW register.
| #define NRF24L01_SETUP_AW_REG_BITS_AW (uint8_t)0x03 |
AW[1:0] bits in SETUP_AW register.
| #define NRF24L01_SETUP_RETR_MASK_REG |
Mask for all defined bits[7:0] in SETUP_RETR register.
| #define NRF24L01_SETUP_RETR_REG_BITS_ARC (uint8_t)0x0F |
ARC[3:0] bits in SETUP_RETR register.
| #define NRF24L01_SETUP_RETR_REG_BITS_ARD (uint8_t)0xF0 |
ARD[7:4] bits in SETUP_RETR register.
| #define NRF24L01_STATUS_MASK_IRQ_FLAGS |
Mask for IRQ[6:4] interrupt flag bits in STATUS register.
| #define NRF24L01_STATUS_MASK_REG |
Mask for all defined bits[6:0] in STATUS register.
| #define NRF24L01_STATUS_REG_BIT_MAX_RT (uint8_t)0x10 |
MAX_RT[4] interrupt flag bit in STATUS register.
| #define NRF24L01_STATUS_REG_BIT_RX_DR (uint8_t)0x40 |
RX_DR[6] interrupt flag bit in STATUS register.
| #define NRF24L01_STATUS_REG_BIT_TX_DS (uint8_t)0x20 |
TX_DS[5] interrupt flag bit in STATUS register.
| #define NRF24L01_STATUS_REG_BIT_TX_FULL (uint8_t)0x01 |
TX_FULL[0] flag bit in STATUS register.
| #define NRF24L01_STATUS_REG_BITS_RX_P_NO (uint8_t)0x0E |
RX_P_NO[3:1] pipe number bits in STATUS register.
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